1. Field of the Invention
The present invention relates generally to a method of forming integrated circuit structures. In particular, the present invention relates to a method of forming fin structures in integrated circuits.
2. Description of the Prior Art
In recent years, as various kinds of consumer electronic products are constantly improved and miniaturized, the size of the semiconductor components have accordingly reduced, in order to meet requirements of high integration, high performance, and low power consumption.
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (Fin FET) have been developed to replace the planar MOS transistors. The three-dimensional structure of a fin FET increases the overlapping area between the gate and the fin structure of the silicon substrate, the channel region is therefore accordingly more effectively controlled. The drain-induced barrier lowering (DIBL) effect and the short channel effect are therefore reduced. The channel region is also longer for an equivalent gate length, thereby increasing the current between the source and the drain. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
To manufacture non-planar FET device, numerous protruding and parallel fin structures must be formed firstly on semiconductor substrate, and deposition, planarization, and etch back processes are then performed on the substrate to form shallow trench isolations (STI) between the fin structures. The height of the fin structure is also defined in this step. During the formation of the fin structures, the etch back process is commonly used in a conventional approach by using diluted hydrofluoric (DHF) acid to etch the STI structures between the fin structures until a predetermined depth is reached, thereby forming the fin structures. However, some disadvantages are found in the fin structures formed by using the conventional approach. For example, the width difference of top surface and bottom surface of the fin structure is larger (ex. larger than 1 nm), the corner of fin structures and surrounding STI structures will have significant wicking features (ex. the height difference between the top surface of the STI adjacent to the fin structure and the top surface of the STI away from the fin structure may exceed 40 Å), and the top surface of resulting fin structures may not be provided with corner rounding feature, so that additional H2 annealing process is necessary to obtain a corner rounding feature. The above-mentioned disadvantages may impact the performances of resulting non-planar FET devices, or may increase the production time and costs.
Accordingly, the present invention is directed to improve the above-mentioned conventional method in order to obtain better fin structures and simplify the process steps.